AI-Assisted Hardware Security Verification: A Survey and AI Accelerator Case Study
arXiv SecurityArchived Apr 03, 2026✓ Full text saved
arXiv:2604.01572v1 Announce Type: new Abstract: As hardware systems grow in complexity, security verification must keep up with them. Recently, artificial intelligence (AI) and large language models (LLMs) have started to play an important role in automating several stages of the verification workflow by helping engineers analyze designs, reason about potential threats, and generate verification artifacts. This survey synthesizes recent advances in AI-assisted hardware security verification and
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Computer Science > Cryptography and Security
[Submitted on 2 Apr 2026]
AI-Assisted Hardware Security Verification: A Survey and AI Accelerator Case Study
Khan Thamid Hasan, Md Ajoad Hasan, Nashmin Alam, Md. Touhidul Islam, Upoma Das, Farimah Farahmandi
As hardware systems grow in complexity, security verification must keep up with them. Recently, artificial intelligence (AI) and large language models (LLMs) have started to play an important role in automating several stages of the verification workflow by helping engineers analyze designs, reason about potential threats, and generate verification artifacts. This survey synthesizes recent advances in AI-assisted hardware security verification and organizes the literature along key stages of the workflow: asset identification, threat modeling, security test-plan generation, simulation-driven analysis, formal verification, and countermeasure reasoning. To illustrate how these techniques can be applied in practice, we present a case study using the open-source NVIDIA Deep Learning Accelerator (NVDLA), a representative modern hardware design. Throughout this study, we emphasize that while AI/LLM-based automation can significantly accelerate verification tasks, its outputs must remain grounded in simulation evidence, formal reasoning, and benchmark-driven evaluation to ensure trustworthy hardware security assurance.
Comments: This paper will be presented at IEEE VLSI Test Symposium (VTS) 2026
Subjects: Cryptography and Security (cs.CR)
Cite as: arXiv:2604.01572 [cs.CR]
(or arXiv:2604.01572v1 [cs.CR] for this version)
https://doi.org/10.48550/arXiv.2604.01572
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From: Khan Thamid Hasan [view email]
[v1] Thu, 2 Apr 2026 03:37:18 UTC (75 KB)
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