logical $T$ gates in the recent BB architecture paper

logical T 𝑇 gates in the recent BB architecture paper Ask Question Asked 9 months ago Modified today Viewed 92 times 6 I’m reading the recent IBM paper arXiv:2506.03094 and it is unclear on how they complete their logical T 𝑇 gate implementation. In surface codes, each T 𝑇 gate typically requires real-time decoding and a correction operation dependent on the decoder’s output, either applying a logical S 𝑆 gate, or modifying a measurement basis (e.g., as in Litinski’s auto-corrected π/8 π / 8 rotation) if there are sufficient physical resources. However, this crucial step seems missing or not explicitly described in the paper. My guess is that it could be incorporated into their magic state factory or handled by their “local processing unit” (LPU), but the details aren’t clear. How and where the real-time feedback is used? Does anyone know how the correction for the logical T 𝑇 gate is performed in their approach? error-correctionfault-tolerance Share Improve this question Follow edited 1 hour ago Ohad 1,9414 4 silver badges 15 15 bronze badges asked Jun 27, 2025 at 9:52 Yaniv Kurman 711 1 bronze badge Add a comment Know someone who can answer? Share a link to this question via email, Twitter, or Facebook. Your Answer Sign up or log in Sign up using Google Sign up using Email and Password Post as a guest Name Email Required, but never shown Post Your Answer By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy. Start asking to get answers Find the answer to your question by asking. Ask question Explore related questions error-correctionfault-tolerance See similar questions with these tags. The Overflow Blog Multi-stage attacks are the Final Fantasy bosses of security Related 5 Magic state distillation with the 15 qubit code. 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