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General circuit compilation protocol into partially fault-tolerant quantum computing architecture

arXiv Quantum Archived Mar 19, 2026 ✓ Full text saved

arXiv:2603.17428v1 Announce Type: new Abstract: As we are entering an early-FTQC era, circuit execution protocols with logical qubits and certain error-correcting codes are being discussed. Here, we propose a circuit execution protocol for the space-time efficient analog rotation (STAR) architecture. Gate operations within the STAR architecture is based on lattice surgery with surface codes, but it allows direct execution of continuous gates $Rz(\theta)$ as non-Clifford gates instead of $T = Rz(

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    Quantum Physics [Submitted on 18 Mar 2026] General circuit compilation protocol into partially fault-tolerant quantum computing architecture Tomochika Kurita As we are entering an early-FTQC era, circuit execution protocols with logical qubits and certain error-correcting codes are being discussed. Here, we propose a circuit execution protocol for the space-time efficient analog rotation (STAR) architecture. Gate operations within the STAR architecture is based on lattice surgery with surface codes, but it allows direct execution of continuous gates Rz(\theta) as non-Clifford gates instead of T = Rz(\pi/4). Rz(\theta) operations involve creation of resource states |m_\theta \rangle = \frac{1}{\sqrt{2}} (|0 \rangle + e^{i\theta} |1\rangle ) followed by ZZ joint measurements with target logical qubits. While employing Rz(\theta) enables more efficient circuit execution, both their creations and joint measurements are probabilistic processes and adopt repeat-until-success (RUS) protocols which are likely to result in considerable time overhead. Our circuit execution protocol aims to reduce such time overhead by parallel trials of resource state creations and more frequent trials of joint measurements. By employing quadratic unconstrained binary optimization (QUBO) in determining resource state allocations within the space, we successfully make our protocol efficient. Furthermore, we proposed performance estimators given the target circuit and qubit topology. It successfully predicts the time performance within less time than actual simulations do, and helps find the optimal qubit topology to run the target circuits efficiently. Subjects: Quantum Physics (quant-ph) Cite as: arXiv:2603.17428 [quant-ph]   (or arXiv:2603.17428v1 [quant-ph] for this version)   https://doi.org/10.48550/arXiv.2603.17428 Focus to learn more Submission history From: Tomochika Kurita [view email] [v1] Wed, 18 Mar 2026 07:08:56 UTC (1,899 KB) Access Paper: HTML (experimental) view license Current browse context: quant-ph < prev   |   next > new | recent | 2026-03 References & Citations INSPIRE HEP NASA ADS Google Scholar Semantic Scholar Export BibTeX Citation Bookmark Bibliographic Tools Bibliographic and Citation Tools Bibliographic Explorer Toggle Bibliographic Explorer (What is the Explorer?) Connected Papers Toggle Connected Papers (What is Connected Papers?) Litmaps Toggle Litmaps (What is Litmaps?) scite.ai Toggle scite Smart Citations (What are Smart Citations?) Code, Data, Media Demos Related Papers About arXivLabs Which authors of this paper are endorsers? | Disable MathJax (What is MathJax?)
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    arXiv Quantum
    Category
    ◌ Quantum Computing
    Published
    Mar 19, 2026
    Archived
    Mar 19, 2026
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