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Optimizing Logical Mappings for Quantum Low-Density Parity Check Codes

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arXiv:2603.17167v1 Announce Type: new Abstract: Early demonstrations of fault tolerant quantum systems have paved the way for logical-level compilation. For fault-tolerant applications to succeed, execution must finish with a low total program error rate (i.e., a low program failure rate). In this work, we study a promising candidate for future fault-tolerant architectures with low spatial overhead: the Gross code. Compilation for the Gross code entails compiling to Pauli Based Computation and t

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    Quantum Physics [Submitted on 17 Mar 2026] Optimizing Logical Mappings for Quantum Low-Density Parity Check Codes Sayam Sethi, Sahil Khan, Maxwell Poster, Abhinav Anand, Jonathan Mark Baker Early demonstrations of fault tolerant quantum systems have paved the way for logical-level compilation. For fault-tolerant applications to succeed, execution must finish with a low total program error rate (i.e., a low program failure rate). In this work, we study a promising candidate for future fault-tolerant architectures with low spatial overhead: the Gross code. Compilation for the Gross code entails compiling to Pauli Based Computation and then reducing the rotations and measurements to the Bicycle ISA. Depending on the configuration of modules and the placement of code modules on hardware, one can reduce the amount of resulting Bicycle instructions to produce a lower overall error rate. We find that NISQ-based, and existing FTQC mappers are insufficient for mapping logical qubits on Gross code architectures because 1. they do not account for the two-level nature of the logical qubit mapping problem, which separates into code modules with distinct measurements, and 2. they naively account only for length two interactions, whereas Pauli-Products are up to length n, where n is the number of logical qubits in the circuit. For these reasons, we introduce a two-stage pipeline that first uses hypergraph partitioning to create in-module clusters, and then executes a priority-based algorithm to efficiently assign clusters onto hardware. We find that our mapping policy reduces the error contribution from inter-module measurements, the largest source of error in the Gross Code, by up to \sim36\% in the best case, with an average reduction of \sim13\%. On average, we reduce the failure rates from inter-module measurements by \sim22\% with localized factory availability, and by \sim17\% on grid architectures, allowing hardware developers to be less constrained in developing scalable fault tolerant systems due to software driven reductions in program failure rates. Comments: 15 pages, 19 figures Subjects: Quantum Physics (quant-ph) Cite as: arXiv:2603.17167 [quant-ph]   (or arXiv:2603.17167v1 [quant-ph] for this version)   https://doi.org/10.48550/arXiv.2603.17167 Focus to learn more Submission history From: Sayam Sethi [view email] [v1] Tue, 17 Mar 2026 21:53:58 UTC (1,972 KB) Access Paper: HTML (experimental) view license Current browse context: quant-ph < prev   |   next > new | recent | 2026-03 References & Citations INSPIRE HEP NASA ADS Google Scholar Semantic Scholar Export BibTeX Citation Bookmark Bibliographic Tools Bibliographic and Citation Tools Bibliographic Explorer Toggle Bibliographic Explorer (What is the Explorer?) Connected Papers Toggle Connected Papers (What is Connected Papers?) Litmaps Toggle Litmaps (What is Litmaps?) scite.ai Toggle scite Smart Citations (What are Smart Citations?) Code, Data, Media Demos Related Papers About arXivLabs Which authors of this paper are endorsers? | Disable MathJax (What is MathJax?)
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    arXiv Quantum
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    ◌ Quantum Computing
    Published
    Mar 19, 2026
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    Mar 19, 2026
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