Triple-Hoisted Baby-Step Giant-Step Linear Transformation over CKKS Homomorphic Encryption and Hardware Accelerator
arXiv SecurityArchived May 19, 2026✓ Full text saved
arXiv:2605.17222v1 Announce Type: new Abstract: Computations can be directly carried out over ciphertexts using homomorphic encryption (HE), which is indispensable for privacy-preserving cloud computing. Linear transformation is widely used in neural networks, including large language models. However, the implementation of linear transformation over HE requires a large number of ciphertext rotations, which incur significant memory and hardware overhead despite existing simplification techniques.
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Computer Science > Cryptography and Security
[Submitted on 17 May 2026]
Triple-Hoisted Baby-Step Giant-Step Linear Transformation over CKKS Homomorphic Encryption and Hardware Accelerator
Sajjad Akherati, Xinmiao Zhang
Computations can be directly carried out over ciphertexts using homomorphic encryption (HE), which is indispensable for privacy-preserving cloud computing. Linear transformation is widely used in neural networks, including large language models. However, the implementation of linear transformation over HE requires a large number of ciphertext rotations, which incur significant memory and hardware overhead despite existing simplification techniques. This paper proposes a triple-hoisted baby-step giant-step algorithm that decomposes the baby step further to substantially reduce the number of ciphertext rotations needed for the CKKS HE evaluation of linear transformation. Moreover, to reduce off-chip memory access, which contributes to the majority of the latency, a memory-optimized data path is proposed by partitioning the algorithm into multiple phases. Furthermore, an efficient FPGA-based hardware accelerator with an optimized permutation circuit for message routing is designed for the proposed scheme. For a set of typical parameters, the proposed design reduces the off-chip memory access by 2.9x compared to the best prior design. Synthesized for Xilinx Virtex UltraScale+ devices, the proposed design achieves a 5.8x reduction in computational latency compared with the baseline design.
Comments: 11 pages, 6 figures, 7 tables, 34 refrences, and journal paper
Subjects: Cryptography and Security (cs.CR)
Cite as: arXiv:2605.17222 [cs.CR]
(or arXiv:2605.17222v1 [cs.CR] for this version)
https://doi.org/10.48550/arXiv.2605.17222
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Submission history
From: Sajjad Akherati [view email]
[v1] Sun, 17 May 2026 01:57:35 UTC (455 KB)
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