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Secure Authentication in Wireless IoT: Hamming Code Assisted SRAM PUF as Device Fingerprint

arXiv Security Archived Apr 20, 2026 ✓ Full text saved

arXiv:2604.15810v1 Announce Type: new Abstract: Static Random Access Memory (SRAM) Physically Unclonable Functions (PUFs) make use of intrinsic manufacturing variations in memory cells to derive device-unique responses. Employing such hardware-rooted fingerprints for authentication, this work demonstrates a threshold-based authentication proof of concept for constrained Industrial Internet of Things (IIoT) devices. The proposed scheme can reliably cap the the post-authentication bit error rate (

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    Computer Science > Cryptography and Security [Submitted on 17 Apr 2026] Secure Authentication in Wireless IoT: Hamming Code Assisted SRAM PUF as Device Fingerprint Florian Lehn, Pascal Ahr, Hans D. Schotten Static Random Access Memory (SRAM) Physically Unclonable Functions (PUFs) make use of intrinsic manufacturing variations in memory cells to derive device-unique responses. Employing such hardware-rooted fingerprints for authentication, this work demonstrates a threshold-based authentication proof of concept for constrained Industrial Internet of Things (IIoT) devices. The proposed scheme can reliably cap the the post-authentication bit error rate (BER) below 1 %. Inherent SRAM PUF unreliability is addressed by a resource-efficient combination of Hamming code (HC) Error Correction (EC) and Temporal Majority Voting (TMV). Increasing HC redundancy or TMV count significantly reduces the BER, albeit with diminishing returns and increasingly prohibitive computational overhead. Furthermore, this work quantifies the threshold gap between strict reliability and security constraints. This gap is reframed as a design budget which enables the resource-aware calibration of the acceptance threshold, PUF response length, and stabilization technique, without violating designed-for error limits. Larger responses make reliability optimizations increasingly obsolete. This comparative analysis establishes a comprehensive design space for PUF EC, guiding future implementations in balancing EC quality against resource constraints such as computational demand, power consumption, and implementation complexity. Comments: This is a preprint submitted to arXiv, licensed under arXiv.org perpetual, non-exclusive license. This work is accepted but not yet published at the 30th ITG-Symposium, Mobile Communications - Technologies and Applications in Osnabrueck, Germany Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR) Cite as: arXiv:2604.15810 [cs.CR]   (or arXiv:2604.15810v1 [cs.CR] for this version)   https://doi.org/10.48550/arXiv.2604.15810 Focus to learn more Submission history From: Pascal Ahr [view email] [v1] Fri, 17 Apr 2026 08:09:02 UTC (10,437 KB) Access Paper: view license Current browse context: cs.CR < prev   |   next > new | recent | 2026-04 Change to browse by: cs cs.AR References & Citations NASA ADS Google Scholar Semantic Scholar Export BibTeX Citation Bookmark Bibliographic Tools Bibliographic and Citation Tools Bibliographic Explorer Toggle Bibliographic Explorer (What is the Explorer?) Connected Papers Toggle Connected Papers (What is Connected Papers?) Litmaps Toggle Litmaps (What is Litmaps?) scite.ai Toggle scite Smart Citations (What are Smart Citations?) Code, Data, Media Demos Related Papers About arXivLabs Which authors of this paper are endorsers? | Disable MathJax (What is MathJax?)
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    arXiv Security
    Category
    ◬ AI & Machine Learning
    Published
    Apr 20, 2026
    Archived
    Apr 20, 2026
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