Resolving Availability and Run-time Integrity Conflicts in Real-Time Embedded Systems
arXiv SecurityArchived Apr 16, 2026✓ Full text saved
arXiv:2511.14088v2 Announce Type: replace Abstract: Run-time integrity enforcement in real-time systems presents a fundamental conflict with availability. Existing approaches in real-time systems primarily focus on minimizing the execution-time overhead of monitoring. After a violation is detected, prior works face a trade-off: (1) prioritize availability and allow a compromised system to continue to ensure applications meet their deadlines, or (2) prioritize security by generating a fault to ab
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Computer Science > Cryptography and Security
[Submitted on 18 Nov 2025 (v1), last revised 15 Apr 2026 (this version, v2)]
Resolving Availability and Run-time Integrity Conflicts in Real-Time Embedded Systems
Adam Caulfield, Muhammad Wasif Kamran, N. Asokan
Run-time integrity enforcement in real-time systems presents a fundamental conflict with availability. Existing approaches in real-time systems primarily focus on minimizing the execution-time overhead of monitoring. After a violation is detected, prior works face a trade-off: (1) prioritize availability and allow a compromised system to continue to ensure applications meet their deadlines, or (2) prioritize security by generating a fault to abort all execution. In this work, we propose PAIR, an approach that offers a middle ground between the stark extremes of this trade-off. PAIR monitors real-time tasks for run-time integrity violations and maintains an Availability Region (AR) of all tasks that are safe to continue. When a task causes a violation, PAIR triggers a non-maskable interrupt to kill the task and continue executing a non-violating task within AR. Thus, PAIR ensures only violating tasks are prevented from execution, while granting availability to remaining tasks. With its hardware approach, PAIR does not cause any run-time overhead to the executing tasks, integrates with real-time operating systems (RTOSs), and is affordable to low-end microcontroller units (MCUs) by incurring +2.3% overhead in memory and hardware usage.
Subjects: Cryptography and Security (cs.CR)
Cite as: arXiv:2511.14088 [cs.CR]
(or arXiv:2511.14088v2 [cs.CR] for this version)
https://doi.org/10.48550/arXiv.2511.14088
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Submission history
From: Adam Caulfield [view email]
[v1] Tue, 18 Nov 2025 03:16:50 UTC (175 KB)
[v2] Wed, 15 Apr 2026 15:53:26 UTC (193 KB)
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