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Enabling Deterministic User-Level Interrupts in Real-Time Processors via Hardware Extension

arXiv Security Archived Apr 07, 2026 ✓ Full text saved

arXiv:2604.04015v1 Announce Type: new Abstract: The growing complexity of real-time embedded systems demands strong isolation of software components into separate protection domains to reduce attack surfaces and limit fault propagation. However, application-supplied device interrupt handlers -- even untrusted -- have to remain in the kernel to minimize interrupt latency, undermining security and burdening manual certifications. Current hardware extensions accelerate interrupts only when the targ

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    Computer Science > Cryptography and Security [Submitted on 5 Apr 2026] Enabling Deterministic User-Level Interrupts in Real-Time Processors via Hardware Extension Hongbin Yang, Huanle Zhang, Runyu Pan The growing complexity of real-time embedded systems demands strong isolation of software components into separate protection domains to reduce attack surfaces and limit fault propagation. However, application-supplied device interrupt handlers -- even untrusted -- have to remain in the kernel to minimize interrupt latency, undermining security and burdening manual certifications. Current hardware extensions accelerate interrupts only when the target protection domain is scheduled by the kernel; consequently, they are limited to improving average-case performance but not worst-case latency, and do not meet the requirements of critical real-time applications such as autonomous vehicles or robots. To overcome this limitation, we propose a novel hardware extension that enables direct, deterministic switching to the appropriate protection domain upon user-level interrupt arrival -- without kernel intervention -- even when that domain is dormant. Our hardware extension reduces worst-case latency by more than 50x with a 19% increase in core area (2% of total die area) and 4.1% increase in dynamic power. To the best of our knowledge, this is the first integrated mechanism to guarantee user-level interrupt delivery with a nanosecond-scale yet bounded worst-case latency. Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR) Cite as: arXiv:2604.04015 [cs.CR]   (or arXiv:2604.04015v1 [cs.CR] for this version)   https://doi.org/10.48550/arXiv.2604.04015 Focus to learn more Submission history From: Runyu Pan [view email] [v1] Sun, 5 Apr 2026 08:25:43 UTC (536 KB) Access Paper: HTML (experimental) view license Current browse context: cs.CR < prev   |   next > new | recent | 2026-04 Change to browse by: cs cs.AR References & Citations NASA ADS Google Scholar Semantic Scholar Export BibTeX Citation Bookmark Bibliographic Tools Bibliographic and Citation Tools Bibliographic Explorer Toggle Bibliographic Explorer (What is the Explorer?) Connected Papers Toggle Connected Papers (What is Connected Papers?) Litmaps Toggle Litmaps (What is Litmaps?) scite.ai Toggle scite Smart Citations (What are Smart Citations?) Code, Data, Media Demos Related Papers About arXivLabs Which authors of this paper are endorsers? | Disable MathJax (What is MathJax?)
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    arXiv Security
    Category
    ◬ AI & Machine Learning
    Published
    Apr 07, 2026
    Archived
    Apr 07, 2026
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